“The design revolves around the sampling bandwidth. All designs should avoid using some or all of the highest frequency portion of the rated full power bandwidth, otherwise the dynamic performance (SNR/SFDR) will degrade and change drastically. To determine the sampling bandwidth of a high-speed ADC, the examples in the text should be used, as these data are not always available from the data sheet.

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Today we are going to talk about the bandwidth accuracy of the ADC. Without further ado, let’s go straight to the topic↓↓↓

ADC Settling Time Accuracy

Generally speaking, the internal front end of an ADC needs to settle within half a cycle or a sampling clock cycle (0.5/Fs), so as to provide an accurate representation of the internal analog signal capture. Therefore, for a 12-bit ADC with a sampling rate of 2.5 GSPS and a full-scale input range of 1.3 V pp, the full power bandwidth (FPBW) can be derived from the following transient equation:

Solve for t:

Substitute τ = 1/(2 × π × FPBW), a time constant, to solve for FPBW:

Now, let t = 0.5/Fs, the time required for the sample to set up is as follows (sample period is 1/Fs):

This minimizes the bandwidth or FPBW required for the ADC’s internal front end. This is the bandwidth required for the converter’s internal front end to settle to within 1 LSB and to sample the analog signal correctly. To meet the 1 LSB accuracy requirement of this type of ADC, this will take several time constants.

A time constant is 24 ps or τ = 1/(2 × π × FPBW). To understand the number of time constants required to meet the LSB size requirements over the ADC’s full-scale range, it is necessary to find the full-scale error or %FS.

or 1 LSB = FS/(2N), where N = number of bits;
or 1.3 V pp/(212) = 317 mV pp, and %FS = (LSB/FS) × 100 = 0.0244.

By plotting the Euler number, or eτ, a curve can be drawn so that the relative error can be easily seen each time the constant is passed. As can be seen in Figure 1, it takes 8.4 time constants for a 12-bit ADC sample to settle to within about 1 LSB.

Figure 1. Establishing Accuracy vs. Time Constant

In this way, designers can estimate the maximum analog input frequency or sampling bandwidth for the converter and still settle to within 1 LSB error. Beyond this range, the ADC cannot accurately represent the signal. This can be simply defined as:

FMAX = 1/(τ × number of time constants)

or

1/(24 ps × 8.4) = 4.96 GHz

Remember that the best-case scenario is represented here and assumes a single-pole ADC front end. Not all real-life converters work this way, but it’s a good start.

A brief note on ADC bandwidth

The ADC full power bandwidth is different from the defined converter usable bandwidth or sampling bandwidth. It can be regarded as the full power bandwidth (FPBW) of the analog signal input to the op amp. The signal is more like a triangle wave signal, and there is a lot of distortion at the output.

FPBW is the bandwidth required by the ADC to accurately capture the signal and allow the internal front end to settle correctly (6.62 GHz in the previous example). It is not a good idea to choose an IF and use the converter in that range, as the performance results of the system can vary widely; at about 5 GHz, the full-scale bandwidth is much higher based on the rated resolution and performance specifications in the converter’s data sheet the maximum sampling bandwidth of the converter itself.

The design revolves around the sampling bandwidth. All designs should avoid using some or all of the highest frequency portion of the rated full power bandwidth, otherwise the dynamic performance (SNR/SFDR) will degrade and change drastically. To determine the sampling bandwidth of a high-speed ADC, the examples in the text should be used, as these data are not always available from the data sheet.

Often, data sheets specify or even list the production-tested frequencies within the converter’s sampling bandwidth that guarantee rated performance. However, in older ADC products these test frequencies were not always defined in FMAX in the data sheet. In the future, these bandwidth terms in the industry will need to be better explained, defined and tested.