[Introduction]Compared with static and single screen Display, eclectic dynamic and carousel screens have stronger expressiveness and visual impact. The ever-increasing resolution and picture quality undoubtedly put forward higher requirements for the display solution performance of the integrators. In the traditional display technology, the control performance and control scheduling ability of the main control MCU are increasingly dwarfed. FPGA chips, which have faster data processing capabilities and are easy to program, have entered people’s field of vision and gradually occupied a place in the display market.
In an environment with strict timeliness requirements, FPGAs can demonstrate outstanding computing power and strong data processing capabilities. FPGA is especially suitable for high-definition digital television (HDTV), such as various types of Displays, projectors, set-top boxes, home networks and other application scenarios. The current mainstream display control systems mostly use FPGA chips or FPGAs combined with other chips as the main control chips. With its high-quality features such as low latency, high throughput, and high flexibility, FPGA chips can easily cope with the data format conversion requirements of various types of displays, and realize the customization of displays of various shapes and sizes.
Anlu’s SF1 series FPSoC®
SHANGHAI ANLOGIC INFOTECH CO.,LTD.
As an FPGA chip design enterprise dedicated to innovation and independent research and development, Anlu Technology has been deeply involved in the research and development and design of FPGA chips and dedicated EDA software for many years. Its SF1 series FPSoC® is a device product for consumer electronics and industrial fields. It can provide a high-performance, low-power solution integrating FPGA and CPU functions for the development and rapid application of downstream customers in the industry chain.
SF1 series FPSoC® integrates RISC-V CPU hard core, 2 DSI hard cores, DSC hard core and 128Mbit PSRAM, data exchange between CPU and FPGA can be carried out through AHB bus, built-in two four-channel MIPI hard cores provide up to 17.6 The MIPI data transceiver capability of Gbps bandwidth supports the ultra-small package of 4.5×4.5mm2. At the same time, the CPU also integrates 2 SPI, I2C, UART and GPIO. The perfect interface makes the SF1 series FPSoC® have good compatibility for various applications.
The SF1S60CG121I device can realize the function of dynamically displaying multiple pictures, in which the CPU is responsible for reading and storing multiple pictures from the SD card to the PSRAM, and the FPGA is responsible for reading the multiple pictures from the PSRAM in sequence, and finally the picture-in-picture The way of superimposing with the video source is sent to the LCD display screen through DSI for display.
This solution shows how to superimpose and display video images based on a single SF1 device, and also provides a template for the combined use of CPU and FPGA.
● SF1 single-chip solution reduces system development cost
● FPGA and CPU complement each other’s advantages, taking into account flexibility and high performance
● Adopt mature development platform to help products go to market quickly
The whole scheme design deeply integrates the working characteristics of CPU and FPGA. The control part with variable functions but low real-time performance is implemented by CPU, and the display logic part with single function but high real-time performance is implemented by FPGA. The flexibility and real-time performance are greatly improved compared to a single CPU or FPGA. Because of this, users can flexibly decompose tasks in practical application development to create more possibilities.
Source: Anlu Technology
The Links: LQ104S1DG35 LQ9D340H