Programmable DSP” title=”DSP”>DSP architecture for TD-SCDMA” title=”TD-SCDMA”>TD-SCDMA and TD-LTE” title=”TD-LTE”>TD-LTE design
As the largest mobile market in the world, China hopes to formulate standards different from those of European and American countries for the development of mobile standards. That is, the current 3G standard TD-SCDMA and the future 4G standard TD-LTE.
In early 2006, the Chinese government announced that TD-SCDMA has officially become China’s 3G mobile communication standard. In 2009, China Mobile, the world’s largest mobile operator, announced that it would provide 3G services based on TD-SCDMA standards. Meanwhile, China Unicom and China Telecom will launch 3G services based on WCDMA and CDMA-2000 standards respectively. This means that there will be 3 different 3G networks in China at the same time in the next time.
Obviously, the launch of 3G services in China is much later than that of European and American countries. China Mobile realizes that it is impossible to rely only on TD-SCDMA to ensure its current leading position. Therefore, China Mobile has set its sights on the future 4G standard LTE when launching TD-SCDMA. Therefore, China Mobile may also skip 3G as soon as possible and then evolve to LTE.
Based on the current situation, it is difficult to predict exactly which standard will dominate the future Chinese mobile market. Therefore, as a terminal baseband chip supplier, it is currently facing a very difficult choice. If you only develop for a certain standard, you may bet on the wrong standard. However, if you design a baseband that supports multiple standards, the traditional baseband design method based on hardware accelerators will greatly increase the difficulty, cost, and risk of development, and lack sufficient flexibility. In this case, engineers will naturally look for programmable solutions that provide sufficient flexibility while reducing the time required to develop multiple standards.
Different Approaches to Wireless Baseband Design
Generally, the wireless baseband is designed in the following three ways:
• Traditional hardware approach – The baseband is all implemented in hardware. This approach basically allows the first chip to be brought to market very quickly. At the same time, this design ensures the lowest power consumption. However, chips designed in this way are completely inflexible and difficult to upgrade to support subsequent products.
• Software-defined radio mode – implemented in a completely soft baseband mode, the same chip can support multiple different standards in software. This method only needs to switch the software to support different standards, and does not need to change the design of the chip at all. However, the main problem of this method is the complexity of the programmable engine design and the high power consumption compared to the hardware method.
• Hybrid – DSP plus hardware accelerators. In this way, the processing part of the baseband that needs flexibility can be implemented on the DSP in software, and the rest of the processing parts that are computationally intensive and relatively fixed, such as FFT, can be implemented in the form of hardware accelerators.
Considering the high risk brought by pure hardware design, this paper mainly discusses two other programmable baseband design methods.
Figure 1 CEVA-XC” title=”CEVA-XC”>CEVA-XC block diagram
Figure 2 CEVA-X1641 block diagram
Software Radio Design Method Based on CEVA-XC
The CEVA-XC is a high-performance communications processor optimized for the most advanced wireless standards (see Figure 1 for a block diagram). Based on the CEVA-X architecture, the CEVA-XC can fully support multiple advanced wireless standards in software, including the most complex 4G standards LTE Cat.5 and WiMAX II (IEEE 802.16m), as well as 3G and 3.5G. This innovative processor is capable of running multiple different wireless standards simultaneously in a purely soft baseband fashion.
A CEVA-XC can simultaneously support multiple different wireless standards in software, thus eliminating the need for hardware accelerators designed for different standards. Therefore, the power consumption and area of the entire system can be reduced.
The CEVA-XC architecture can contain 1, 2 or 4 vector processors. Each vector processor is a 3-issue, single-instruction-multiple-data (SIMD) engine that can process 256-bit wide data. It contains 16 MAC units, arithmetic, logic and shift units. The CEVA-XC instruction set can handle the processing requirements of 4G baseband, such as matrix processing, MIMO detectors, complex filtering, data permutations and bit processing.
Hybrid baseband design method based on CEVA-X1641
CEVA-X represents a family of general-purpose high-performance DSP processors that are widely used in wireless baseband applications and have been mass-produced in products from multiple baseband chip suppliers.
CEVA-X is based on Very Long Instruction Word (VLIW) and Single Instruction Multiple Data (SIMD) architectures. VLIW allows multiple instructions to execute concurrently to ensure a high degree of instruction-level parallelism while maintaining low power consumption. The CEVA-X architecture has good support for the C language, which can help developers greatly reduce development costs and shorten time to market.
The CEVA-X1641 is a member of the CEVA-X family (see Figure 2 for a block diagram). It has four 16-bit wide MACs. The CEVA-X1641 can run at 700MHz in the worst case at 65nm.
As a high-performance and easy-to-program DSP, CEVA-X1641 allows designers to flexibly divide hardware and software into their terminal baseband SOC designs. Different baseband customers use different hardware and software partitions and single DSP cores or multiple DSP cores in their designs. In addition, the customer’s software investment and software reuse in future evolution products are guaranteed. Currently, multiple CEVA customers are designing their 4G wireless basebands using the CEVA-X1641.
It is precisely because of the reality of multi-standard coexistence in China’s wireless market in the future that it is necessary to use the same platform to support multiple different standards. Whether it is a pure soft baseband method based on software radio or a hybrid programmable method, it can provide enough flexibility to meet the needs of repeated use and rapid time-to-market.
For a long time, the leaders of the wireless baseband market have made it clear that programmable is the direction of wireless baseband development. The two CEVA DSP cores discussed in this paper have realized the provision of suitable solutions according to the different requirements of authorized customers for chip architecture and flexibility.
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