[Introduction]In the previous articles of this series, we introduced the main system requirements of the electric vehicle fast charging system, outlined the key stages in the system development process, and met the team of engineers involved in the design of the 25 kW SiC DC fast charging system. .
Now, let’s take a closer look at the 25 kW SiC fast charging design. In Parts 1 and 2 we talked about the chosen specification, topology and market background, today we will focus on the simulation of the AC-DC conversion part, as well as what was previously called “Three-Phase Active Rectification” part, referred to as PFC.
As mentioned in the first part, power simulation helps to verify assumptions before designing and building a hardware system and discover possible problems in device selection, PCB layout, and even post-testing. For example, simulation helps us test the operation of voltage, current, switching frequency, losses, heat dissipation, and control algorithms.
In addition to verification, simulation results help address other important steps in the design process, such as passive device selection. An effective simulation flow can reduce the debugging and hardware consumption of the product development cycle, and speed up the whole process.
Preparation before simulation
Before the simulation starts, it is also very important to prepare in advance. Below is a list of the preparations we think are the most important, and how to deal with them.
It is very important to think about the simulation goals in advance. Goals affect the details of building a simulation model, which we will focus on in the next section. In this project, PFC’s power simulation helped the design team to solve the following problems:
● Perform functional verification of PFC before hardware design
● Confirm that the DC output voltage, current, and power of the working node should meet other system requirements.
● Confirm that the efficiency value can meet the target at 70 kHz switching frequency
● Estimated power consumption
● Confirmed the gate resistance value of the gate driver (the starting value of Demo)
● Confirmed the parameters of the PFC Inductor (can be sent to the inductor supplier to speed up the supply cycle)
● Confirmed electrolytic capacitor parameters based on current ripple (critical value), ESR, capacitance and voltage
Power Simulation Models and Software
The simulation model is the key to the whole process. The model reproduces the function and parameters of each device in the circuit. Each device in the model, such as switches, diodes, gate drivers, and passive devices, can be augmented with varying degrees of detail. Of course there are also devices that are difficult to model. A complex set of models can be more time-consuming to run, and simpler models can be simulated under many different system conditions to address different problems.
The development shortcut for this system is to simplify the model, thereby speeding up the simulation and design process. Of course, the accuracy of the model is very critical and will greatly affect the results. Device models that do not affect functional and electrical parameters have been simplified, and key devices have been modeled more accurately.
Power supply simulations are often based on existing SPICE models. In this project, we used SIMetrix, a mixed-mode simulation software that provides powerful simulation capabilities for fast convergence.
The last essential element of simulation is to evaluate those specific devices and parameters. Such simulations can help us provide the best combination of these parameters to meet the system requirements. In this design, we believe that the most important components are:
1. PFC inductor. The parameters of the PFC inductor should be determined as early as possible according to the application requirements, input voltage, power and current. Secondly, we should consider its size and cost performance. The design team calculated and estimated that the inductance value should be within tens of μH.
2. Output capacitor. The selection of capacitors is based on loop current and ripple voltage. Since the voltage of the DC bus is high (about 1000 V), we need several electrolytic capacitors in series to correspond to the high bus voltage.
3. Switching frequency. The frequency value is predetermined by the given inductance value and grid requirements. As mentioned in Part II, 70 Hz is the solution that meets both efficiency and EMI requirements.
The initial values of these parameters confirmed by various methods are verified by simulation. Methods used to determine initial values include: standard volumetric design calculations, borrowing from existing designs, historical documents, and drawings. Using in-depth analysis of these methods, it is possible to make educated guesses about the parameters, which we will refer to again in the simulation results that follow.
In this section, we will introduce the simulation model (submodel) established for this design, and focus on explaining the model characteristics and the content that has been overlooked. In addition, there are actions taken for models that are not foundational or necessary. At the end is a summary table.
Figure 1 shows the simulation model in SIMetrix, including the power part (top) and the PWM part (bottom). Follow-up will bring the content of the algorithm.
The PWM modulation loop is based on a typical space vector pulse width modulation algorithm (SVPWM), which simplifies the control loop and makes it addressable through the PI regulator. We used the measured main phase voltage as the controller input to simplify the model, whereas in the actual hardware system, we need to use a phase locked loop in the digital domain to measure the instantaneous supply reference voltage.
Figure 1. SIMetrix model of the PFC section
Bus and bus network models
The power model consists of 3 configurable bus bars that produce 50/60 Hz sinusoids with a phase difference of 120°. The initial phase can be changed, which is useful for verifying the inrush current protection loop of the input. For convenience, most of the loads in the simulation model are resistive loads.
As part of the simulation, we need basic, differential-mode conducted interference (CE) verification against input filtering, either by inserting an artificial mains network (AMN, Artificial Mains Network) or an impedance stabilization network (LISN, between the power supply and the filter, Line Impedance Stabilization Network, according to CISPR22). We are not discussing this topic in this series. The model of the grid also includes the AC grid impedance that affects the control, so adding the simulation can improve the accuracy of the simulation.
Input filtering is the first part of the converter. We will not do any input filtering model design for this simulation, so a simplified model is used (Figure 2). As mentioned in the second part, that is an off-the-shelf model.
Adding filtering components to this simulation brings two benefits. First, the output impedance of the filter is part of the PFC control loop, without which it is difficult to get a reliable PFC loop. Not considering EMI filtering at the design stage will eventually cause trouble for your product.
Second, to get a more accurate simulation of efficiency and thermal management, we also added the power loss of the filter to the simulation. Again, one of the goals of this simulation is to validate our control scheme and the device that will affect the performance of the final product.
Figure 2. Input Filter Loop Model
Inrush current protection
Inrush current protection is a critical part of EV charging systems, and we also need to simulate this part. The implementation of this model is not complicated, a typical three-phase system, in which two phases are formed by resistors and relays in parallel, as shown in Figure 3. Since the system does not involve the neutral, there is no need to add resistance to the third phase. (Resistor R in Figure 1 represents the equivalent resistance resulting from the connection.)
Figure 3. Inrush Current Protection Model
In general, the simulation of inrush current can verify the maximum energy dissipation due to the resistance, which can help to select the correct components.
PFC Inductor Model
SPICE simulation software can provide its own inductor model, but it is relatively simple and cannot reflect the important characteristics of inductors in power systems, such as self-saturation and self-resonance effects. The model we built in Figure 4 contains these important parts. The inductor saturation effect is referred to a look-up table that provides the relationship between relative magnetic susceptibility (μr) and magnetic field strength (H). Winding losses are represented by a series resistor. Figure 4 illustrates more details about these elements in the model.
Figure 4. Inductor model with saturation and self-resonance effects.
The saturation effect (inductance changes with different operating currents) is modeled according to the look-up table and the magnetic design standard formula: (1) L = μ0 μr (Ae/Le) N², (2) H = (N × I)/Le (3) lookup table μr = f(H), (4) VL = L × dI/dt, B1 is the inductor voltage. L and dI/dt are derived from formula (1) and formula (4) respectively based on the test inductance L1 (1H). F1 is a current driven current source with a 1:1 turns ratio with an output equal to the inductance model measurement. Since L1 = 1H, dI/dt = V (dI_dt-REF). F1 has no effect on the inductance model and is only used to derive dI/dt in the system where VL, PFC are calculated at each point. L (B1, F1 and L1), Cp and Rp simulate the self-resonant characteristics of the inductor.
power section model
The power part is the focal point of the whole power conversion and the key of the simulation model. It contains 3 half-bridge SiC Modules and gate drivers. The drive system has a fairly significant impact on overall performance (more so for SiC-based systems), so we strongly recommend including it in the overall simulation, even if only partially. However, the current problem is that the existing gate driver models are often designed to be more complex in order to adapt to more common ones. Generally speaking, for the system-level simulation, or the simulation of this project, a simplified driving model is sufficient.
Although the IV relationship will not be reflected in detail in the drive parameter table, we can obtain an approximation of the output characteristics by using the drive output parameters (maximum output/sink current) and rise and fall times corresponding to specific points, thereby improving the Simulation accuracy and an acceptable computation time. We use this method to simulate the gate driver NCD57000. (Figure 5)
Figure 5. Power Section Model for Phase A
Modeling SiC MOSFETs in power modules is obviously a critical step in the overall simulation. As with gate drivers, there are also models of SiC MOSFETs with considerable detail, these are often used for device characterization and extraction of device parameters under any operating conditions.These models extend the information often presented in datasheets under characteristic operating points
However, in our simulation models, we need 6 different switching devices, and these models make the simulation quite slow. Convergence issues also arise frequently. So in this case, we can take a pragmatic approach: create a simplified model that contains the main elements and features that have a huge impact on the overall system. (Image 6)
Figure 6. Simplified MOSFET model
The model in the above figure can reflect the following key parameters of SiC MOSFET: 3 main parasitic capacitances, RDS(ON)and body diode voltage drop VF. These are not individual values, but characteristic curves for different operating situations.
Note that parasitic capacitance parameters vary with VDSchanges with the change. VDSThe characteristic table of the is often provided in the product manual, but some derivation calculations are required. We use the following equation to calculate the model value, and the three parasitic parameters are denoted by CISSCOSSand CRSSexpress.
● Cgd = CRSS
● Cgs = CISS –CRSS
● Cds = COSS –CRSS
Figure 7 shows the simulation model used in this project. The nonlinear curve of the capacitance value is based on the parameter comparison table.
Figure 7. Cgd‘s model. Cgsand CdsThe models are the same, but the capacitance values are different.
R of SIC MOSFETDS(ON)largely depends on the gate voltage VGS, whose properties are included in the model of “B_rds”. Although VGSto RDS(ON)has a great influence, but it also varies with the instantaneous I to a certain extent.Dand VDSchange, but in this simulation, the effect of this feature is not considered.
Body diode VF– The current characteristics can be modeled simply by building a voltage-current look-up table. The current flowing through the diode and the body diode ground voltage drop VFrelated. Body diode VFThe characteristics may not be useful for all applications, but in three-phase PFC, the body diode is quite important in the rectifier circuit, and its VF-current characteristics can significantly affect the setting of the switching dead zone, so in the whole system Very important. The diode’s reverse recovery characteristics are not considered in this simulation.
It should be emphasized that the basic SiC MOSFET model does not include the parasitic inductance and resistance caused by the PIN pin. So adding a built-in resistor can better reproduce the switching characteristics (dV/dt) to select or optimize the gate resistance. Second, to accurately reproduce voltage spikes during operation, modeling parasitic inductances is highly recommended, but is less critical for system-level verification, and we can optimize switching characteristics by tuning gate resistors in practice.
Table 1 summarizes the content of the simulation model and the output of each part of the simulation. The final actual results should satisfy the simulation results and solve the design problems we envisioned.
Table 1. Summary of Simulation Models: Parts Included in Simulation and Reflected in Simulation Models
After the laborious task of building a simulation model, we fast-forward to the fun part—using and evaluating the conclusions.
To address our problem, we performed a series of simulations based on the variables summarized in Figure 2. In the following, we present the results obtained, our observations on these results, and design decisions based on these results.
All of these explanations and instructions are summarized in Table 3 at the end of this chapter for clarity.
Efficiency of the PFC section
System efficiency is critical to the overall simulation results. Figure 8, Figure 9 and Figure 10 present the efficiency values and associated losses. As we expected, higher input voltages lead to higher overall efficiency because IPHASEdecreased (Figure 8).
For the results brought by different inductances, it can be seen that higher inductance values may lead to higher efficiency. However, there are many other devices that can affect the results. It demonstrates the benefits of simulation, as efficiency calculations and device considerations at different operating nodes are very tedious. Figure 10 provides details on the winding losses; the difference in winding losses due to different inductance values is smaller than the difference in system losses.
Figure 8. Efficiency of PFC Section vs. Input Voltage, Inductance, and Output Capacitance
Figure 9. PFC section loss versus input voltage, inductance, and output capacitance
Figure 10. Inductor Loss in PFC Section vs. Input Voltage, Inductance, and Output Capacitance
The simulation yielded interesting information about the losses in the power module (Figure 11). The loss of the module is only related to the inductance value. The reason should be that a lower inductance value will bring a larger ripple current. The larger the ripple current, the lower the on-current, so the switching loss is also reduced.
Figure 11. Overall loss of PIM module versus input voltage, inductance, and output capacitance
However, there is no direct connection between the power module and the inductance value, because the adjustment process and PWM also have an impact. Simulations based on actual models can help predict conclusions even if the actual relationship cannot be directly determined.
The most interesting finding is the distribution of losses due to multiple elements (devices) in the model (Figure 12). This distribution map can help us figure out where the loss comes from and which parts need attention to improve efficiency. In this design, we have proved that the system efficiency will be greater than 98% in all cases, so there is no problem with the efficiency. With these results, we can choose the solution that best meets the needs of the rest of the system.
Figure 12. Schematic diagram of losses. The main condition of the simulation is VIN=230 V, POUT=26.5 kW, VOUT=800 V, the inductance and capacitance are 245 μH and 4×470 μF. The simulation time is 50ms. When calculating the energy loss, the time setting basically considers 30ms to 50ms (represented by “30ms % 50ms”) to ensure that the system runs in a stable stage.
Inrush Current Simulation
The main purpose of the inrush current control simulation is to confirm the peak and current rms value, and the losses due to the current limiting resistor at startup. This simulation can help us to verify the selection of the current limiting resistor.
In general, the peak phase current (within 100 μs) at startup is limited to several times the rated value. Likewise, the maximum phase current rms value can also be limited by setting a waiting period (several seconds) before repeated starts.
Figures 13 and 14 show the worst-case results for our system: bus phase-to-zero voltage is 310 Vrms, phase A is shifted -30° from zero, and the 450 μF output capacitor is completely depleted. Simulation tells us that repeated starts should set a cooldown of 4.19 seconds to ensure the 7 W dissipation requirement (power dissipation of the anti-surge resistor). However, in general the charging system does not re-start within a short period of time (within a few seconds).
Figure 13. Inrush current protection. Worst case, power loss (top) and energy dissipation (bottom) waveforms at startup, C at surge protectionOUT=450 μF, VIN=310Vac. The surge protection consists of 2 33Ω resistors in series for each phase (4 resistors in total). Red line: One anti-surge resistor power and energy (A phase). Blue line: One anti-surge resistor power and energy (B phase). Phase A and Phase B are dissipated by 24.81J and 29.29J of energy, respectively, and the cooling time under the power consumption limit of 7W is 3.55 seconds and 4.19 seconds, respectively.
Figure 14. Inrush current protection. Input current of phase A and B and PFC output voltage during inrush current protection. Same as Figure 13, with protection current and COUTrelated.
Power factor is a key requirement, and EV fast charging regulations require that the power factor must reach 0.99 under full load. Figure 15 verifies that all designs meet power factor requirements, and Figure 16 presents a perfect sinusoidal current waveform along with IPHASE-VINPHASErelation.
No matter how the sense value changes, IPHASE,RMSIt remains almost constant (Figure 17), which is consistent with the overall efficiency results (Figure 8), as the variation between the different models of inductance is also very small. A slightly larger change can be observed in the peak current (Figure 18), but IPHASE,PEAKvalue is not critical for power loss because IPHASE,RMSIt is the main factor used to estimate losses and efficiencies.
It is certain that the greater the current, the greater the system losses. This is also reflected in the Total Harmonic Distortion (THD) results (Figure 19).
Figure 15. Power factor versus input voltage, inductance, and output capacitance. Power factor >0.99 in all cases.
Figure 16. Phase current curve, PFC inductor 245 μH. PFC A-phase power factor 0.999, VIN=230V.
Figure 17. Input current rms versus input voltage, inductance, and output capacitance.
Figure 18. Peak input current versus input voltage, inductance, and output capacitance.
Figure 19. Input current total harmonic distortion (THD) versus input voltage, inductance, and output capacitance.
PFC Inductor Operating Conditions
As mentioned in Table 1, a thorough understanding of the inductor current is helpful in designing a PFC inductor with excellent performance. To design or select a suitable inductor, we need to consider the following 4 key current values, all of which can be obtained by simulation.
● IPHASE,RMSto solve the heat dissipation problem (Figure 17)
● IPHASE,PEAKcalculate the magnetic saturation of the core (Figure 18)
● IRIPPLE,PEAK-PEAKto estimate the core loss (core loss is not included in this simulation, but it is recommended to calculate it separately)
● VPHASE,PEAKwhich defines the insulation class of the windings
Figure 20 shows that at different VPHASE-NEUTRALThe peak-to-peak value of the inductor ripple current. The ripple current at 245 μH is 40% smaller than that at 130 μH. Another detail is that we know the actual I through simulationRIPPLE,PEAK-PEAKHow to reach the maximum and minimum values at the zero crossings and vertices of the waveform. Figures 21 and 22 illustrate these differences.
We can also see that the actual ripple current curve and the shape of the frequency are different at the same point. This situation is relatively common in SVM and does not cause problems. (We won’t discuss this in depth in this article, but it is related to the transformation process in CCM and DCM.)
Inductor design needs to consider the maximum peak-to-peak ripple current. Another important factor in designing an inductor is the withstand voltage of the inductor. Figures 23 and 24 represent these values.
Figure 20. Inductor Ripple Current vs. Input Voltage, Inductance, and Output Capacitance
Figure 21. Detail of inductor current with peak current sinusoidal waveform. Conditions: Phase B, VIN=230 V, POUT=26.5kW, LPFC=245 μH. Waveform parameters: IPHASE,RMS=38.9 A, IPHASE,PEAK-PEAK=4.1A. X-axis: 10 μs/div.
Figure 22. Detail of inductor current at zero crossing of current sinusoidal waveform. Conditions: Phase B, VIN=230 V, POUT=26.5kW, LPFC=245 μH. Waveform parameters: IPHASE,RMS=38.9 A, IPHASE,PEAK-PEAK=5.58A. X-axis: 10 μs/div.
Figure 23. Peak Inductor Voltage vs. Input Voltage, Inductance, and Output Capacitance.
Figure 24. PFC inductor voltage envelope simulation. Typical system waveforms using SVPWM.
Voltage between busbar and DC output
In three-phase PFC systems and inverters, a voltage difference can occur between the phase conductors, neutral conductor (N), ground conductor (PE), and the DC negative output (-VDC) of the converter because the front and rear parts of the system are not Electrical isolation (in the PFC section). So this possibility must be considered during simulation and development.
Figure 25 is the voltage envelope of the input and negative DC output (-VDC), and the voltage difference between neutral or ground and the negative DC output. Figure 26 and Figure 27 show the voltage increase from -300 V to +1100 V. We need to at least take these voltage levels into account when designing the inductor and PCB. Such high voltages can cause isolation problems between components and inductors on the PCB. In addition, the high voltage and dV/dt between the neutral/ground and the DC negative output will bring different types of noise, especially the system connected to the PFC output is particularly susceptible to common mode noise.
Later in the hardware testing and evaluation phase, high voltages between neutral/ground and the negative output voltage may require extra care and additional safety measures. Simulation once again played an important role in revealing the problems that had to be solved, helping us achieve robust designs and benefiting the development process in the future.
Interestingly, the envelope of the neutral/ground to DC output GND voltage is affected by three times the grid frequency, and the modulation depth is related to the saturation of the PFC inductor (Figure 25). These phenomena are influenced by the PWM modulation strategy, which in our case corresponds to the envelope seen in the SVPWM system.
Figure 25. Phase Voltage and Neutral/Ground to DC Output Ground Voltage Envelope
Figure 26. Maximum Voltage Difference (a) and Minimum Voltage Difference (b) from Phase A to DC Negative Output (-VDC) vs. Input Voltage, Inductance, and Output Capacitance
Figure 27. The relationship between the maximum voltage difference (a) and the minimum voltage difference (b) from the ground wire to the negative DC output (-VDC) and the input voltage, inductance and output capacitance
PFC output inductance
After power factor correction, the main job of the PFC system is to boost the DC bus voltage (boost dc-link voltage) and keep it at the reference value. The DC bus capacitor acts as a boost capacitor and also needs to effectively handle the current ripple generated when the load is connected to the output. Simulation can help us understand how these two variables (DC bus voltage and ripple current) will change once the actual hardware system is built.
Figure 28 tells us that the output current of the capacitor does not change drastically with changes in the inductance or capacitance value. In addition, ±10% of the input phase voltage VPHASEThe variation results in a ripple current variation of approximately ±15% (Figure 29).
The output AC voltage component (VPEAK-PEAK) and the input phase voltage VPHASENot relevant, but affected by DC output capacitance and parasitic equivalent resistance (ESR). Figure 30 demonstrates that 4 times VPEAK-PEAKIn the worst case, four 470 μF capacitors are connected in parallel.
Figure 28. Output Capacitor Current ICAPACITOR,RMSRelationship with input voltage value, inductance value and output capacitance value
Figure 29. Typical output inductor waveform. Condition: VIN=230 V, POUT=26.5kW
Result: ICAPACITOR,PEAK-PEAK=58 A,ICAPACITOR,PEAK=25A,ICAPACITOR,RMS=24.78A. X-axis: 10 μs/div.
Figure 30. Output Capacitor Ripple Voltage Input Voltage, Inductance, and Output Capacitance
Switch Transitions: On and Off
A key parameter to verify the switching performance of the PFC section is the switching speed (Figure 31), or the dV/dt of the MOSFET. In theory, the faster the switching speed, the lower the losses and the higher the efficiency. However, there are still other factors that limit the switching speed. For example, the ability of the switch itself to withstand such high gradient transitions or common mode (CM) noise from EMI or other fast switching.
Figure 31. Turn-On Waveform of PFC MOSFET
Figure 32 shows that in the configuration presented in this simulation, the dV/dt value exceeds 66 V/ns, a high-speed switch that is only possible with wide-bandgap technology. In practice, such a high dV/dt still carries a high risk (even for SiC modules) that ultra-high overvoltage spikes from parasitic inductances can easily exceed the device’s upper withstand voltage limit.
Figure 32. Low-Side Phase A SiC MOSFET Switching Speed vs. Input Voltage, Inductance, and Output Capacitance
Adjusting the gate resistance is the easiest way to reduce dV/dt. A larger gate resistor value reduces switching speed and reduces overall design risk, but also brings the disadvantage of a small power loss (since the switching speed is not as fast). Based on the conclusion of this simulation, we decided to make a compromise solution and replace the gate resistor with a larger value (1.8 Ω—>4.7 Ω) to ensure that the dV/dt of the MOS transistor is 25 V/ns when it is turned on. about. This will be used as the initial value when verifying the actual hardware board.
Another factor that affects switching efficiency is turn-on current. Figure 33 shows the turn-on current obtained in the simulation. However, the efficiency of the system has been proven before, and no major modifications to the opening method are foreseen at this time.
Figure 33. Low-Side Low-Side Phase A SiC MOSFET Maximum Turn-On Current vs. Input Voltage, Inductance, and Output Capacitance
As for turn-off transitions, we took a similar approach. Figures 34, 35 and 36 show the results of these simulations. The turn-off process is also fast (up to 40 V/ns) when using a 100 kΩ sink resistor. In the test board, we also increased the resistance to keep the turn-off dV/dt level to around 25 V/ns.
Figure 34. Turn-off waveform of PFC MOSFET
Figure 35. Low-Side Low-Side Phase A SiC MOSFET Maximum Turn-On Current vs. Input Voltage, Inductance, and Output Capacitance
Figure 36. Low-Side Phase A SiC MOSFET Switching Speed vs. Input Voltage, Inductance, and Output Capacitance
Simulation Results and Conclusions
One of the ultimate goals of simulation is to reduce the number of hardware iterations and speed up the mass production of new products. Through this article, we can clearly understand the importance of setting a goal before simulating and designing a model. The results of the simulation will help answer our open questions, validate our hypotheses, or uncover necessary modifications for the operation or optimization of the system. Table 3 summarizes the results of the above simulations.
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